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12:51:27",{"stem":204,"path":205,"title":206,"date":207,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F3.HDL\u002FLecture6","\u002Fugcourses\u002Fjunior-autumn\u002Fhdl\u002Flecture6","Lecture 6：Behavioral Modeling，非阻塞赋值","2026-09-10 12:51:12",{"stem":209,"path":210,"title":211,"date":212,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F3.HDL\u002FPPTCorrespondence","\u002Fugcourses\u002Fjunior-autumn\u002Fhdl\u002Fpptcorrespondence","与PPT的对应","2026-09-10 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3;\nend\n\u002F\u002F阻塞赋值:a的赋值必须在b赋值开始前完成\n","verilog","",[461,462,457],"code",{"__ignoreMap":459},[446,464,297],{"id":297},[270,466,467],{},"当前时间步结束时，会对于顺序块进行并行赋值。",[399,469,471],{"id":470},"当前时间表结束时的含义","‘当前时间表结束时’的含义",[270,473,474],{},"模拟器根据事件的特点，处理对于给定时间的所有事件",[476,477,478,500,503],"ol",{},[479,480,481,482],"li",{},"执行以下操作：\n",[483,484,485,488,491,494,497],"ul",{},[479,486,487],{},"计算所有赋值的右边",[479,489,490],{},"赋值所有过程阻塞赋值的左边",[479,492,493],{},"赋值所有连续赋值的左边",[479,495,496],{},"计算所有原语(如: 门电路)的输入和输出",[479,498,499],{},"对于$display语句进行打印",[479,501,502],{},"赋值所有过程非阻塞赋值的左边",[479,504,505,506,591],{},"根据",[409,507,510,552],{"className":508},[509],"katex",[409,511,514],{"className":512},[513],"katex-mathml",[515,516,518],"math",{"xmlns":517},"http:\u002F\u002Fwww.w3.org\u002F1998\u002FMath\u002FMathML",[519,520,521,547],"semantics",{},[522,523,524,528,531,534,537,540,543],"mrow",{},[525,526,527],"mi",{},"s",[525,529,530],{},"t",[525,532,533],{},"r",[525,535,536],{},"o",[525,538,539],{},"b",[525,541,542],{},"e",[544,545,546],"mtext",{},"、",[548,549,551],"annotation",{"encoding":550},"application\u002Fx-tex","strobe、",[409,553,557],{"className":554,"ariaHidden":556},[555],"katex-html","true",[409,558,561,566,571,574,578,581,584,587],{"className":559},[560],"base",[409,562],{"className":563,"style":565},[564],"strut","height:0.6944em;",[409,567,527],{"className":568},[569,570],"mord","mathnormal",[409,572,530],{"className":573},[569,570],[409,575,533],{"className":576,"style":577},[569,570],"margin-right:0.0278em;",[409,579,536],{"className":580},[569,570],[409,582,539],{"className":583},[569,570],[409,585,542],{"className":586},[569,570],[409,588,546],{"className":589},[569,590],"cjk_fallback","monitor语句的执行进行打印",[446,593,594],{"id":594},"赋值语句的执行",[399,596,597],{"id":597},"例1",[453,599,602],{"className":600,"code":601,"language":458,"meta":459},[456],"reg[7:0]a,b;\ninitial b = 0;\ninitial a = 4;\nalways @(a or b)\n    begin\n        a = b + 2;\n        b = a * 3;\n    end\n\u002F\u002Fa = 0 + 2 = 2\n\u002F\u002Fb = 2 * 3 = 6\n",[461,603,601],{"__ignoreMap":459},[453,605,608],{"className":606,"code":607,"language":458,"meta":459},[456],"reg[7:0] a,b;\ninitial b = 0;\ninitial a = 4;\nalways @(a or b)\n    begin\n        a \u003C= b + 2;\n        b \u003C= a * 3;\n    end\n\u002F\u002Fa = 0 + 2 = 2\n\u002F\u002Fb = 4 * 3 = 12\n",[461,609,607],{"__ignoreMap":459},[399,611,613],{"id":612},"例2-对于寄存器的赋值","例2  对于寄存器的赋值",[615,616,617],"h6",{"id":617},"对于寄存器的阻塞赋值",[453,619,622],{"className":620,"code":621,"language":458,"meta":459},[456],"module fsm_mod(q1, q0, in, clk);\n    output q1, q0;\n    input clk, in;\n    reg q1, q0;\n    always @(posedge clk) begin\n        q1 = in;\n        q0 = in | q1;\n    end\nendmodule\n",[461,623,621],{"__ignoreMap":459},[270,625,626],{},"上述代码波形图如下：",[270,628,629],{},[431,630],{"alt":433,"src":631},"\u002Fimg\u002FHDL\u002FLecture6-03.png",[270,633,634],{},"对于使用同一个@posedge或者@negedge的时钟的级联信号而言，它相当于组合逻辑",[270,636,637],{},[431,638],{"alt":433,"src":639},"\u002Fimg\u002FHDL\u002FLecture6-04.png",[615,641,642],{"id":642},"对于寄存器的非阻塞赋值",[453,644,647],{"className":645,"code":646,"language":458,"meta":459},[456],"module fsm_mod(q1, q0, in, clk);\n    output q1, q0;\n    input clk, in;\n    reg q1, q0;\n    always @(posedge clk) begin\n        q1 \u003C= in;\n        q0 \u003C= in | q1;\n    end\nendmodule\n",[461,648,646],{"__ignoreMap":459},[650,651,652],"blockquote",{},[270,653,654],{},"上述代码波形图",[270,656,657],{},[431,658],{"alt":433,"src":659},"\u002Fimg\u002FHDL\u002FLecture6-05.png",[270,661,662],{},"对于使用同一个@posedge或者@negedge的时钟的级联信号而言，需要加1个寄存器",[270,664,665],{},[431,666],{"alt":433,"src":667},"\u002Fimg\u002FHDL\u002FLecture6-06.png",[399,669,671],{"id":670},"例3-d触发器flip-flop的非阻塞赋值","例3  D触发器（flip-flop）的非阻塞赋值",[270,673,674],{},"在设计与综合阶段，在always块中的非阻塞赋值以行为一致的方式、被用于D触发器建模",[483,676,677,680,683],{},[479,678,679],{},"1个寄存器reg变量被用于表示D触发器",[479,681,682],{},"写入变量(见上例，如：q1或者q0, 使用\u003C=)意味着连接到其D触发器输入",[479,684,685],{},"从变量读取(见上例，如：q1)意味着连接到其D触发器输出",[453,687,690],{"className":688,"code":689,"language":458,"meta":459},[456],"always @(posedge iClock) begin : lLoop \u002F\u002FTestbench\n    if (!rReady) disable lLoop;\n    rData = rTData[nDataIndex][`DataMSB:`DataLSB];\nend\n\nalways @(posedge iClock or negedge iReset) begin \u002F\u002FDesign\n    if (!iReset) rDataUse \u003C= 0;\n    else\n        if (iReset) begin\n        rDataUse \u003C= rData;\n    end\nend\n",[461,691,689],{"__ignoreMap":459},[693,694,696],"h5",{"id":695},"_3个寄存器链常规","3个寄存器链（常规）",[453,698,701],{"className":699,"code":700,"language":458,"meta":459},[456],"module chain(q, i, clk);\n    output q;\n    input i, clk;\nreg q, q1, q2;\nalways @(posedge clk) begin\n    q \u003C= q1;         \u002F\u002F并行所以无关次序\n    q1 \u003C= q2;\n    q2 \u003C= i;\nend\nendmodule\n",[461,702,700],{"__ignoreMap":459},[693,704,706],{"id":705},"多路复用的数据通路方法时序存储组合计算","多路复用的数据通路方法(时序存储+组合计算)",[453,708,711],{"className":709,"code":710,"language":458,"meta":459},[456],"module chain(q, i, clk); \n    output q; \n    input i, clk; \n    reg q, q1, q2; \n    wire q_next, q1_next, q2_next; \n    always @(posedge clk) begin \n    q \u003C= q_next; \n    q1 \u003C= q1_next; \n    q2 \u003C= q2_next; \n    end \n    assign q_next = q1; \n    assign q1_next = q2; \n    assign q2_next = i; \nendmodule\n\u002F\u002Fq、q1、q2相当于不同的数据通路\n",[461,712,710],{"__ignoreMap":459},[693,714,715],{"id":715},"结构化方法",[453,717,720],{"className":718,"code":719,"language":458,"meta":459},[456],"module flipflop(q, i, clk);\n    output q;\n    input i, clk;\n    \u002F\u002F implementation of flipflop ..\nendmodule\n\nmodule chain(q, i, clk);\n    output q;\n    input i, clk;\n    wire q1, q2;\n    flipflop F1(q, q1, clk);\n    flipflop F2(q1, q2, clk);\n    flipflop F3(q2, i, clk);\nendmodule\n",[461,721,719],{"__ignoreMap":459},[274,723,724],{"id":724},"总结",[483,726,727,730,733,736],{},[479,728,729],{},"通常用于在always块中对D触发器类型建模",[479,731,732],{},"模拟多个并发表达式的行为",[479,734,735],{},"可以使用always块中的非阻塞赋值设计诸如: 控制器、数据通路等中的时序逻辑",[479,737,738],{},"通常，不要在同一块中混合非阻塞和阻塞赋值",{"title":459,"searchDepth":740,"depth":740,"links":741},4,[742,746,763],{"id":276,"depth":743,"text":276,"children":744},2,[745],{"id":401,"depth":740,"text":401},{"id":444,"depth":743,"text":444,"children":747},[748,750,753],{"id":448,"depth":749,"text":448},3,{"id":297,"depth":749,"text":297,"children":751},[752],{"id":470,"depth":740,"text":471},{"id":594,"depth":749,"text":594,"children":754},[755,756,757],{"id":597,"depth":740,"text":597},{"id":612,"depth":740,"text":613},{"id":670,"depth":740,"text":671,"children":758},[759,761,762],{"id":695,"depth":760,"text":696},5,{"id":705,"depth":760,"text":706},{"id":715,"depth":760,"text":715},{"id":724,"depth":743,"text":724},[228],"行为级建模中的非阻塞赋值，阻塞与非阻塞赋值的区别","md",null,{"slots":769},{},{"text":771,"minutes":772,"time":773,"words":774},"6 min read",5.34,320400,1068,{"title":206,"description":765},{"loc":205,"images":777},[778,779,780,781,782,783],{"loc":434},{"loc":441},{"loc":631},{"loc":639},{"loc":659},{"loc":667},[785,786,787,788],"非阻塞赋值","行为级建模","HDL","课程笔记","tech","colOd9EueBDOiZuE6EkGBsCpVRF9gOhJLWJl2UiV9K8",[792,793],{"title":216,"path":215,"stem":214,"date":182,"type":789,"children":-1},{"title":201,"path":200,"stem":199,"date":202,"type":789,"children":-1},1789037801542]