[{"data":1,"prerenderedAt":2476},["ShallowReactive",2],{"series:index":3,"content:\u002Fugcourses\u002Fjunior-autumn\u002Fhdl\u002Ffeiqilai2":264,"surround:\u002Fugcourses\u002Fjunior-autumn\u002Fhdl\u002Ffeiqilai2":2473},[4,10,15,20,25,30,35,40,45,50,55,60,65,70,75,80,84,89,94,98,103,108,113,118,123,128,133,138,143,148,153,158,163,168,173,178,183,188,193,198,203,208,213,217,221,225,229,234,239,243,247,251,255,259],{"stem":5,"path":6,"title":7,"date":8,"collapsed":9},"posts\u002F2024\u002FXZZD-Aquire-Score","\u002F2024\u002F10\u002F23\u002FXZZD-Aquire-Score","XZZD_Aquire_Score","2024-10-23 15:08:30",false,{"stem":11,"path":12,"title":13,"date":14,"collapsed":9},"posts\u002F2024\u002Felec-design-contest-2024","\u002F2024\u002F07\u002F07\u002Felec-design-contest-2024","东四——隐秘的角落","2024-07-07 11:44:32",{"stem":16,"path":17,"title":18,"date":19,"collapsed":9},"posts\u002F2024\u002Fmechanics","\u002F2024\u002F07\u002F08\u002Fmechanics","about力学","2024-07-08 14:14:07",{"stem":21,"path":22,"title":23,"date":24,"collapsed":9},"posts\u002F2025\u002F25GElecDesignContest","\u002F2025\u002F08\u002F26\u002F25GElecDesignContest","纪念最好的大二五组 - Soleil 的 电赛回忆录","2025-08-26 11:06:33",{"stem":26,"path":27,"title":28,"date":29,"collapsed":9},"posts\u002F2025\u002FEngineering-Innovation","\u002F2025\u002F01\u002F20\u002FEngineering-Innovation","工程实践与创新能力大赛","2025-01-20 22:20:59",{"stem":31,"path":32,"title":33,"date":34,"collapsed":9},"posts\u002F2025\u002FTOP","\u002F2025\u002F01\u002F20\u002FTOP","置顶","3025-01-20 21:53:36",{"stem":36,"path":37,"title":38,"date":39,"collapsed":9},"posts\u002FUGCourses\u002F1.freshman-spring\u002Fengineering-drawing-notes","\u002F2024\u002F06\u002F30\u002Fengineering-drawing-notes","工程图学期末复习","2024-06-30 21:02:09",{"stem":41,"path":42,"title":43,"date":44,"collapsed":9},"posts\u002FUGCourses\u002F1.freshman-spring\u002Findex","\u002Fugcourses\u002Ffreshman-spring","大一春夏","2024-06-30 19:15:28",{"stem":46,"path":47,"title":48,"date":49,"collapsed":9},"posts\u002FUGCourses\u002F2.sophomore-autumn\u002FComplex-Analysis","\u002F2025\u002F01\u002F21\u002FComplex-Analysis","复变函数与积分变换","2025-01-21 13:23:59",{"stem":51,"path":52,"title":53,"date":54,"collapsed":9},"posts\u002FUGCourses\u002F2.sophomore-autumn\u002FFundamentalsMarxism","\u002F2025\u002F06\u002F06\u002FFundamentalsMarxism","马克思主义基本原理","2025-06-06 00:22:45",{"stem":56,"path":57,"title":58,"date":59,"collapsed":9},"posts\u002FUGCourses\u002F2.sophomore-autumn\u002FMathematical-Modeling","\u002F2024\u002F09\u002F22\u002FMathematical-Modeling","数学建模（课程）","2024-09-22 19:07:42",{"stem":61,"path":62,"title":63,"date":64,"collapsed":9},"posts\u002FUGCourses\u002F2.sophomore-autumn\u002FMicroelectronic-Circuits","\u002F2025\u002F01\u002F20\u002FMicroelectronic-Circuits","电基小子","2025-01-20 23:02:49",{"stem":66,"path":67,"title":68,"date":69,"collapsed":9},"posts\u002FUGCourses\u002F2.sophomore-autumn\u002FMumerical-Analysis","\u002F2024\u002F09\u002F19\u002FMumerical-Analysis","数值分析方法","2024-09-19 17:12:56",{"stem":71,"path":72,"title":73,"date":74,"collapsed":9},"posts\u002FUGCourses\u002F2.sophomore-autumn\u002FProbability-Theory","\u002F2025\u002F01\u002F21\u002FProbability-Theory","概率论与数理统计","2025-01-21 12:52:11",{"stem":76,"path":77,"title":78,"date":79,"collapsed":9},"posts\u002FUGCourses\u002F2.sophomore-autumn\u002Fengineering-training","\u002F2024\u002F09\u002F17\u002Fengineering-training","工程训练","2024-09-17 21:40:26",{"stem":81,"path":82,"title":83,"date":44,"collapsed":9},"posts\u002FUGCourses\u002F2.sophomore-autumn\u002Findex","\u002Fugcourses\u002Fsophomore-autumn","大二秋冬",{"stem":85,"path":86,"title":87,"date":88,"collapsed":9},"posts\u002FUGCourses\u002F2.sophomore-autumn\u002Fsolid-state-physics","\u002F2024\u002F09\u002F11\u002Fsolid-state-physics","固体物理基础","2024-09-11 19:15:26",{"stem":90,"path":91,"title":92,"date":93,"collapsed":9},"posts\u002FUGCourses\u002F3.sophomore-spring\u002FMaoTheory","\u002F2025\u002F06\u002F12\u002FMaoTheory","毛概","2025-06-12 14:58:16",{"stem":95,"path":96,"title":97,"date":44,"collapsed":9},"posts\u002FUGCourses\u002F3.sophomore-spring\u002Findex","\u002Fugcourses\u002Fsophomore-spring","大二春夏",{"stem":99,"path":100,"title":101,"date":102,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FLecture1","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Flecture1","Lecture 1：摩尔定律与 CMOS","2026-09-09 19:39:00",{"stem":104,"path":105,"title":106,"date":107,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FLecture10","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Flecture10","Lecture 10：从 MOS 电容到 MOSFET","2026-09-10 00:10:00",{"stem":109,"path":110,"title":111,"date":112,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FLecture11","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Flecture11","Lecture 11：亚阈值效应与 MOSFET 尺寸缩放","2026-09-10 00:20:00",{"stem":114,"path":115,"title":116,"date":117,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FLecture12","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Flecture12","Lecture 12：MOSFET 尺寸缩微","2026-09-10 00:30:00",{"stem":119,"path":120,"title":121,"date":122,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FLecture13","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Flecture13","Lecture 13：MOS 新范式","2026-09-10 00:40:00",{"stem":124,"path":125,"title":126,"date":127,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FLecture2","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Flecture2","Lecture 2：半导体基础","2026-09-09 19:39:31",{"stem":129,"path":130,"title":131,"date":132,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FLecture3","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Flecture3","Lecture 3：费米能级、载流子散射与迁移率","2026-09-09 21:00:00",{"stem":134,"path":135,"title":136,"date":137,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FLecture4","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Flecture4","Lecture 4：漂移电流、扩散电流与产生复合","2026-09-09 23:00:00",{"stem":139,"path":140,"title":141,"date":142,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FLecture5","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Flecture5","Lecture 5：PN 结与耗尽区","2026-09-09 23:10:00",{"stem":144,"path":145,"title":146,"date":147,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FLecture6","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Flecture6","Lecture 6：正向偏置 PN 结与理想二极管方程","2026-09-09 23:20:00",{"stem":149,"path":150,"title":151,"date":152,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FLecture7","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Flecture7","Lecture 7：金半接触","2026-09-09 23:40:00",{"stem":154,"path":155,"title":156,"date":157,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FLecture8","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Flecture8","Lecture 8：PN 结在光电领域的应用","2026-09-09 23:50:00",{"stem":159,"path":160,"title":161,"date":162,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FLecture9","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Flecture9","Lecture 9：MOS 电容","2026-09-10 00:00:00",{"stem":164,"path":165,"title":166,"date":167,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FMidtermExam","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Fmidtermexam","期中复习题","2026-09-09 23:30:00",{"stem":169,"path":170,"title":171,"date":172,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002FMockExam","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices\u002Fmockexam","押题密卷","2026-09-10 00:50:00",{"stem":174,"path":175,"title":176,"date":102,"collapsed":177},"posts\u002FUGCourses\u002F4.junior-autumn\u002F1.microelectronic-devices\u002Findex","\u002Fugcourses\u002Fjunior-autumn\u002Fmicroelectronic-devices","微电子器件",true,{"stem":179,"path":180,"title":181,"date":182,"collapsed":177},"posts\u002FUGCourses\u002F4.junior-autumn\u002F2.ICCAD\u002Findex","\u002Fugcourses\u002Fjunior-autumn\u002Ficcad","面向 ICCAD 的软件基础技术","2026-09-10 12:37:00",{"stem":184,"path":185,"title":186,"date":187,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F3.HDL\u002FFeiQilai1","\u002Fugcourses\u002Fjunior-autumn\u002Fhdl\u002Ffeiqilai1","飞起来1.0","2026-09-10 12:51:49",{"stem":189,"path":190,"title":191,"date":192,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F3.HDL\u002FFeiQilai2","\u002Fugcourses\u002Fjunior-autumn\u002Fhdl\u002Ffeiqilai2","飞起来2.0","2026-09-10 12:52:06",{"stem":194,"path":195,"title":196,"date":197,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F3.HDL\u002FFeiQilai3","\u002Fugcourses\u002Fjunior-autumn\u002Fhdl\u002Ffeiqilai3","飞起来3.0","2026-09-10 12:52:12",{"stem":199,"path":200,"title":201,"date":202,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F3.HDL\u002FLecture13","\u002Fugcourses\u002Fjunior-autumn\u002Fhdl\u002Flecture13","Lecture 13：浮点数标准","2026-09-10 12:51:27",{"stem":204,"path":205,"title":206,"date":207,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F3.HDL\u002FLecture6","\u002Fugcourses\u002Fjunior-autumn\u002Fhdl\u002Flecture6","Lecture 6：Behavioral Modeling，非阻塞赋值","2026-09-10 12:51:12",{"stem":209,"path":210,"title":211,"date":212,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002F3.HDL\u002FPPTCorrespondence","\u002Fugcourses\u002Fjunior-autumn\u002Fhdl\u002Fpptcorrespondence","与PPT的对应","2026-09-10 12:52:18",{"stem":214,"path":215,"title":216,"date":182,"collapsed":177},"posts\u002FUGCourses\u002F4.junior-autumn\u002F3.HDL\u002Findex","\u002Fugcourses\u002Fjunior-autumn\u002Fhdl","硬件描述语言原理与应用",{"stem":218,"path":219,"title":220,"date":44,"collapsed":9},"posts\u002FUGCourses\u002F4.junior-autumn\u002Findex","\u002Fugcourses\u002Fjunior-autumn","大三秋冬",{"stem":222,"path":223,"title":224,"date":44,"collapsed":9},"posts\u002FUGCourses\u002F5.junior-spring\u002Findex","\u002Fugcourses\u002Fjunior-spring","大三春夏",{"stem":226,"path":227,"title":228,"date":44,"collapsed":9},"posts\u002FUGCourses\u002Findex","\u002Fugcourses","本科课程",{"stem":230,"path":231,"title":232,"date":233,"collapsed":9},"posts\u002Fubuntu\u002F1.config","\u002Fubuntu\u002Fconfig","ubuntu 系统配置","2025-08-26 19:38:06",{"stem":235,"path":236,"title":237,"date":238,"collapsed":9},"posts\u002Fubuntu\u002F2.cadence\u002F1.mmsim","\u002Fubuntu\u002Fcadence\u002Fmmsim","在 Ubuntu 24.04 上安装 Cadence MMSIM 15.1 的兼容性问题","2026-09-09 14:06:40",{"stem":240,"path":241,"title":242,"date":238,"collapsed":9},"posts\u002Fubuntu\u002F2.cadence\u002F2.innovus","\u002Fubuntu\u002Fcadence\u002Finnovus","Innovus安装",{"stem":244,"path":245,"title":246,"date":238,"collapsed":9},"posts\u002Fubuntu\u002F2.cadence\u002Findex","\u002Fubuntu\u002Fcadence","Ubuntu24.04安装Cadence 系列软件",{"stem":248,"path":249,"title":250,"date":238,"collapsed":9},"posts\u002Fubuntu\u002F3.synopsys","\u002Fubuntu\u002Fsynopsys","Ubuntu 24.04 安装 Synopsys",{"stem":252,"path":253,"title":254,"date":238,"collapsed":9},"posts\u002Fubuntu\u002F4.vivado","\u002Fubuntu\u002Fvivado","Ubuntu 24.04 安装 Vivado 2020.1",{"stem":256,"path":257,"title":258,"date":238,"collapsed":9},"posts\u002Fubuntu\u002F5.migrate","\u002Fubuntu\u002Fmigrate","硬盘迁移系统",{"stem":260,"path":261,"title":262,"date":263,"collapsed":9},"posts\u002Fubuntu\u002Findex","\u002Fubuntu","Ubuntu装进移动硬盘","2025-08-25 19:38:06",{"id":265,"title":191,"body":266,"categories":2417,"collapsed":9,"date":192,"description":2418,"draft":9,"extension":2419,"hideInArchive":177,"hideInList":177,"image":2420,"meta":2421,"navigation":177,"path":190,"permalink":2420,"published":2420,"readingTime":2423,"recommend":2420,"references":2420,"seo":2428,"sitemap":2429,"stem":189,"tags":2467,"type":2471,"updated":192,"__hash__":2472},"content\u002Fposts\u002FUGCourses\u002F4.junior-autumn\u002F3.HDL\u002FFeiQilai2.md",{"type":267,"value":268,"toc":2379},"minimark",[269,273,310,314,319,324,332,339,342,353,363,383,389,397,403,417,423,427,434,440,444,450,456,462,473,479,485,492,498,501,505,511,522,528,531,534,540,544,547,553,557,564,570,574,581,587,589,592,597,600,606,611,616,667,675,677,680,685,690,705,718,748,751,757,760,763,769,774,788,794,803,816,818,823,828,833,836,841,846,934,937,939,942,947,952,955,991,993,996,1001,1006,1009,1014,1024,1108,1114,1119,1163,1166,1172,1195,1197,1200,1205,1210,1213,1233,1239,1241,1244,1249,1254,1256,1283,1294,1296,1299,1304,1309,1322,1325,1385,1410,1416,1421,1423,1426,1431,1436,1450,1467,1472,1478,1483,1493,1495,1498,1503,1508,1511,1565,1611,1613,1742,1752,1879,1884,1899,1902,1907,1912,1915,1926,1928,1931,1936,1941,1946,1951,1954,1960,1962,1965,1970,1975,1996,2002,2005,2010,2013,2042,2044,2047,2052,2057,2066,2069,2077,2096,2098,2197,2200,2205,2210,2216,2219,2229,2231,2234,2239,2244,2251,2261,2263,2294,2296,2299,2304,2309,2315,2351,2363,2368,2371],[270,271,272],"p",{},"这一部分主要是针对后两道题",[274,275,277,283,291,296,301,304],"alert",{"type":276},"tip",[270,278,279],{},[280,281,282],"em",{},"五：典型代码的编写与注释，共2题，每题9分",[270,284,285,286,290],{},"代码示例中的",[287,288,289],"strong",{},"D触发器、全加器、移位器（这三个是重点）","等，对应题型五为主",[270,292,293],{},[287,294,295],{},"Lecture 10里面最后有代码的",[270,297,298],{},[280,299,300],{},"六：简述以下代码的潜在问题，共3题，每题4分",[270,302,303],{},"综合编译中讲述的重点，对应题型六为主",[270,305,306,307],{},"就是",[287,308,309],{},"之前讲到的十七八个问题里面抽三个来考试（回去看看智云",[311,312,313],"h2",{"id":313},"典型代码",[270,315,316],{},[287,317,318],{},"我重写了一遍神的代码，然后加上了注释（感觉可以自己重写一遍，就能记住了",[320,321,323],"h3",{"id":322},"第一部分组合逻辑电路-combinational-logic","第一部分：组合逻辑电路 (Combinational Logic)",[270,325,326,327,331],{},"来自",[328,329,330],"code",{"code":330},"Lecture 10 PPT","，紫色部分是他的重点",[333,334,336],"h4",{"id":335},"全加器",[337,338,335],"mark",{},[270,340,341],{},"这里展示了三种实现1位全加器的方法，它们在功能上是等价的。",[343,344,345],"ol",{},[346,347,348,349,352],"li",{},"使用 ",[328,350,351],{"code":351},"assign"," 连续赋值\n这是最直接的组合逻辑描述方式，适用于简单的逻辑门级描述。",[354,355,361],"pre",{"className":356,"code":358,"language":359,"meta":360},[357],"language-verilog","module full_adder1(\n    input a,\n    input b,\n    input cin,\n    output sum,\n    output cout\n);\n\n    \u002F\u002F 使用assign语句描述\n\n    \u002F\u002F 和是三个输入的异或\n    assign sum = a ^ b ^ cin;\n\n    \u002F\u002F 只要三个输入当中有两个是1，就要产生进位，于是这样写\n    assign cout = (a & b) | (a & cin) | (b & cin);\n\nendmodule\n","verilog","",[328,362,358],{"__ignoreMap":360},[343,364,366],{"start":365},2,[346,367,348,368,371,372,374,375,378,379,382],{},[328,369,370],{"code":370},"always"," 块\n使用 ",[328,373,370],{"code":370}," 块（配合敏感列表 ",[328,376,377],{"code":377},"a or b or cin"," 或 ",[328,380,381],{"code":381},"always @(*)","）也可以实现组合逻辑",[354,384,387],{"className":385,"code":386,"language":359,"meta":360},[357],"module full_adder2(\n    input a,\n    input b,\n    input cin,\n    output reg sum, \u002F\u002F always中的被赋值的变量必须为reg\n    output reg cout\n);\n\n    \u002F\u002F 敏感列表包含所有的信号\n    always @(a or b or cin) \u002F\u002F 当然，更直接的写法就是 always @(*)这里是因为神这么写\n    begin\n        \u002F\u002F 和为异或\n        sum = a ^ b ^ cin;\n        \u002F\u002F 进位为三位中的任意两位与再或\n        cout = (a & b) | (a & cin) | (b & cin);\n    end\n\nendmodule\n",[328,388,386],{"__ignoreMap":360},[343,390,392],{"start":391},3,[346,393,348,394,396],{},[328,395,370],{"code":370}," 块 (带中间变量)\n这种方式与方式二相同，只是使用了中间变量，使进位逻辑更清晰",[354,398,401],{"className":399,"code":400,"language":359,"meta":360},[357],"module full_adder3(\n    input a,\n    input b,\n    input cin,\n    output reg sum, \u002F\u002F always中的被赋值的变量必须为reg\n    output reg cout\n);\n\n    reg m1, m2, m3;\n\n    \u002F\u002F 敏感列表包含所有的信号\n    always @(a or b or cin)\n    begin\n        \u002F\u002F 和为异或\n        sum = a ^ b ^ cin;\n        \u002F\u002F 进位为三位中的任意两位与再或\n        \u002F\u002F 加上中间变量\n        m1 = a & b;\n        m2 = a & cin;\n        m3 = b & cin;\n        cout = (m1 | m2) | m3;\n    end\n\nendmodule\n",[328,402,400],{"__ignoreMap":360},[343,404,406],{"start":405},4,[346,407,408,409,412,413,416],{},"参数化的加法器\n如何使用 ",[328,410,411],{"code":411},"parameter"," 关键字来创建一个",[287,414,415],{},"可配置位宽","的加法器",[354,418,421],{"className":419,"code":420,"language":359,"meta":360},[357],"module AddWithCarryInCarryOut #(\n    parameter NUMBITS = 3 \u002F\u002F 定义一个代表位数的参数\n)(\n    input [NUMBITS : 1] OpdA, \u002F\u002F 3、2、1三位（神从1开始记数 | 哈哈哈笑死了\n    input [NUMBITS : 1] OpdB,\n    input CarryIn,\n    output [NUMBITS : 1] Sum,\n    output CarryOut\n);\n\n    \u002F\u002F 直接用拼接操作计算\n    assign {CarryOut, Sum} = OpdA + OpdB + CarryIn;\n\nendmodule\n",[328,422,420],{"__ignoreMap":360},[333,424,426],{"id":425},"找最高位的-1-priority-encoder","找最高位的 \"1\" (Priority Encoder)",[270,428,429,430,433],{},"这是一个8位输入的",[287,431,432],{},"优先编码器","，用于找到最高位（MSB）的 \"1\" 所在的索引。",[354,435,438],{"className":436,"code":437,"language":359,"meta":360},[357],"module find_ones(\n    input [7:0] x,\n    output [2:0] y\n);\n\n    \u002F\u002F 神用了二分法\n    wire [3:0] data_4;\n    wire [1:0] data_2;\n\n    \u002F\u002F 检查高4位，用\"|\"缩减或\n    \u002F\u002F 等效为assign y[2] = x[7] | x[6] | x[5] | x[4];\n    assign y[2] = |x[7:4];\n    \u002F\u002F 如果高4位有1，则 data_4 选高4位；否则选低4位\n    assign data_4 = y[2] ? x[7:4] : x[3:0];\n    \u002F\u002F 检查data_4的高2位，用\"|\"缩减或\n    assign y[1] = |data_4[3:2];\n    \u002F\u002F 如果data_4的高2位有1，则 data_2 选高2位；否则选低2位\n    assign data_2 = y[1] ? data_4[3:2] : data_4[1:0];\n    \u002F\u002F 检查data_2的高1位\n    assign y[0] = data_2[1];\n\nendmodule\n",[328,439,437],{"__ignoreMap":360},[333,441,443],{"id":442},"找最低位的-1-priority-encoder","找最低位的 \"1\" (Priority Encoder)",[270,445,446,447,449],{},"这是一个",[287,448,432],{},"，用于找到最低位（LSB）的 \"1\" 所在的索引。",[354,451,454],{"className":452,"code":453,"language":359,"meta":360},[357],"module find_one(\n    input [7:0] data,\n    output [2:0] index\n);\n\n    \u002F\u002F 神用了二分法\n    wire [3:0] data_4;\n    wire [1:0] data_2;\n\n    \u002F\u002F 检查低4位 data[3:0]\n    \u002F\u002F ~|data[3:0] (缩减或非)：当且仅当低4位全部为0时，结果为'1'\n    \u002F\u002F index[2] = 1 表示'1'在高4位\n    assign index[2] = ~|data[3:0]; \n    \u002F\u002F 如果 index[2] 为 1 (低4位全0)，则 data_4 选高4位\n    assign data_4 = index[2] ? data[7:4] : data[3:0];\n\n    \u002F\u002F 检查 data_4 的低2位\n    \u002F\u002F index[1] = 1 表示 '1' 在 data_4 的高2位\n    assign index[1] = ~|data_4[1:0];\n    assign data_2 = index[1] ? data_4[3:2] : data_4[1:0];\n\n    \u002F\u002F 检查 data_2 的低1位\n    \u002F\u002F index[0] = 1 表示 '1' 在 data_2 的高1位\n    assign index[0] = ~data_2[0];\n\nendmodule\n",[328,455,453],{"__ignoreMap":360},[333,457,459],{"id":458},"组合移位器-case-语句",[337,460,461],{},"组合移位器 (Case 语句)",[270,463,464,465,468,469,472],{},"这是一个4位的",[287,466,467],{},"逻辑左移","移位器，使用 ",[328,470,471],{"code":471},"case"," 语句（多路选择器 MUX）实现。",[354,474,477],{"className":475,"code":476,"language":359,"meta":360},[357],"module left_shifter_case(\n    input [3:0] data,\n    input [1:0] ctrl,\n    output reg [3:0] out \u002F\u002F 在always块中赋值，定义为reg\n);\n\n    \u002F\u002F always @(*)表明这是一个组合逻辑块\n    always @(*)\n    begin\n        case(ctrl)\n            2'b00: out = data; \u002F\u002F 不移位\n            2'b01: out = {data[2:0], 1'b0}; \u002F\u002F 左移1位\n            2'b10: out = {data[1:0], 2'b00}; \u002F\u002F 左移2位\n            default: out = {data[0], 3'b000}; \u002F\u002F 左移3位\n        endcase\n    end\n\nendmodule\n",[328,478,476],{"__ignoreMap":360},[333,480,482],{"id":481},"组合移位器-中间变量",[337,483,484],{},"组合移位器 (中间变量)",[270,486,487,488,491],{},"这是一个32位的",[287,489,490],{},"桶形移位器 (Barrel Shifter)","，使用多级三目运算符实现，效率很高。",[354,493,496],{"className":494,"code":495,"language":359,"meta":360},[357],"module left_shift_middle32(\n    input [31:0] data,\n    input [4:0] ctrl,\n    output reg [31:0] out\n);\n\n    reg [31:0] temp;\n\n    \u002F\u002F 核心逻辑就是二进制数的分解，5bit刚好可以表达32位\n    always@(data or ctrl)\n    begin\n        \u002F\u002F 第0级：由 ctrl[0] 控制是否移1位\n        temp = ctrl[0] ? {{data[30:0]}, 1'b0} : data;\n        \u002F\u002F 第1级：由 ctrl[1] 控制是否移2位\n        temp = ctrl[1] ? {{temp[29:0]}, 2'b0} : temp;\n        \u002F\u002F 第2级：由 ctrl[2] 控制是否移4位\n        temp = ctrl[2] ? {{temp[27:0]}, 4'b0} : temp;\n        \u002F\u002F 第3级：由 ctrl[3] 控制是否移8位\n        temp = ctrl[3] ? {{temp[23:0]}, 8'b0} : temp;\n        \u002F\u002F 第4级：由 ctrl[4] 控制是否移16位\n        temp = ctrl[4] ? {{temp[15:0]}, 16'b0} : temp;\n        out = temp;\n    end\n\nendmodule\n",[328,497,495],{"__ignoreMap":360},[499,500],"hr",{},[320,502,504],{"id":503},"第二部分时序逻辑电路-sequential-logic","第二部分：时序逻辑电路 (Sequential Logic)",[333,506,508],{"id":507},"d-触发器-带异步复位",[337,509,510],{},"D 触发器 (带异步复位)",[270,512,513,514,517,518,521],{},"这是所有时序逻辑中最基本、最重要的单元。它在时钟上升沿锁存输入 ",[328,515,516],{"code":516},"d"," 的值，并具有一个",[287,519,520],{},"异步","复位功能。",[354,523,526],{"className":524,"code":525,"language":359,"meta":360},[357],"module d_flip_flop(\n    input clk,\n    input rst,\n    input d,\n    output reg q\n);\n\n    always @(posedge clk or negedge rst)\n    begin\n        if (!rst) begin\n            q \u003C= 0; \u002F\u002F 异步复位\n        end else begin\n            q \u003C= d;\n        end\n    end\n\nendmodule\n",[328,527,525],{"__ignoreMap":360},[333,529,530],{"id":530},"移位寄存器",[270,532,533],{},"包含两个模块：一个4位串行输入、并行输出 (SIPO) 移位寄存器和一个32位并行加载寄存器。",[354,535,538],{"className":536,"code":537,"language":359,"meta":360},[357],"module block4(\n    input clk,\n    input d_in,\n    output reg Q0,\n    output reg Q1,\n    output reg Q2,\n    output reg Q3\n);\n\n    \u002F\u002F 数据在时钟沿从 din -> Q0 -> Q1 -> Q2 -> Q3 移动\n    always@(posedge clk)\n    begin\n        Q0 \u003C= d_in; \u002F\u002F 使用非阻塞赋值\n        Q1 \u003C= Q0;\n        Q2 \u003C= Q1;\n        Q3 \u003C= Q2;\n    end\n\nendmodule\n\nmodule shifter32(\n    input clk,\n    input [32:0] a,\n    output reg [32:0] c\n);\n\n    \u002F\u002F 在每个时钟上升沿\n    \u002F\u002F 寄存器 c 会锁存 a 左移8位、低位补0的结果\n    always @(posedge clk)\n    begin\n        c \u003C= {a[23:0], 8'b0};\n    end\n\nendmodule\n",[328,539,537],{"__ignoreMap":360},[333,541,543],{"id":542},"_1位计数器-可串联","1位计数器 (可串联)",[270,545,546],{},"这是一个1位的计数器单元，包含时序逻辑（DFF）、下一状态逻辑和输出逻辑三部分。",[354,548,551],{"className":549,"code":550,"language":359,"meta":360},[357],"module counter1bit(\n    input clk,\n    input reset,\n    input cin,\n    output cout,\n    output reg bit \u002F\u002F 状态寄存器\n);\n\n    reg bitnext; \u002F\u002F 下一状态\n\n    \u002F\u002F 时序逻辑部分 D触发器\n    always @(posedge clk or negedge reset)\n    begin\n        if (!reset)\n            bit \u003C= 0;\n        else\n            bit \u003C= bitnext;\n    end\n\n    \u002F\u002F 组合逻辑部分，下一状态的逻辑\n    always @(bit or cin)\n    begin\n        \u002F\u002F bitnext = bit XOR cin (T触发器逻辑)\n        \u002F\u002F cin=1 时翻转, cin=0 时保持\n        bitnext = bit ^ cin;\n    end\n\n    \u002F\u002F 组合逻辑部分，进位输出\n    always @(bit or cin)\n    begin\n        \u002F\u002F cout = bit AND cin\n        \u002F\u002F 当本位为1且有进位时，向高位输出进位\n        cout = bit & cin;\n    end\n\nendmodule\n",[328,552,550],{"__ignoreMap":360},[333,554,556],{"id":555},"定时器-timer","定时器 (Timer)",[270,558,559,560,563],{},"这是一个5位的计数器，带异步复位和同步预置，计数到16时停止并拉高 ",[328,561,562],{"code":562},"done"," 信号。",[354,565,568],{"className":566,"code":567,"language":359,"meta":360},[357],"module timerTick(\n    input clk,\n    input reset,\n    input preset,\n    output reg [4:0] tick,\n    output reg done\n);\n\n    always @(posedge clk or negedge reset)\n    begin\n        if (!reset) \u002F\u002F 异步复位，最高优先级\n        begin\n            tick \u003C= 5'b0;\n            done \u003C= 0;\n        end else\n        begin\n            if (preset) \u002F\u002F 同步预置\n            begin\n                tick \u003C= 5'b0;\n                done \u003C= 0;\n            end else\n            begin \u002F\u002F 正常计数逻辑\n                if (tick \u003C 16)\n                begin\n                    tick \u003C= tick +1'b1;\n                    done \u003C= 0;\n                end else\n                begin\n                    tick \u003C= 5'b0;\n                    done \u003C= 1;\n                end\n            end\n        end\n    end\n\nendmodule\n",[328,569,567],{"__ignoreMap":360},[333,571,573],{"id":572},"寄存器文件-register-file","寄存器文件 (Register File)",[270,575,576,577,580],{},"一个简易的",[287,578,579],{},"寄存器文件","（RAM），具有一个同步读\u002F写端口。",[354,582,585],{"className":583,"code":584,"language":359,"meta":360},[357],"module RegFileWithMemory #(\n    parameter N = 2, \u002F\u002F N=2, 地址位宽 (2 bits, 可寻址 2^2=4 个)\n    parameter M = 2 \u002F\u002F M=2, 数据位宽 (2 bits, 2 bits)\n)(\n    input Clk,\n    input wire Readwrite,        \u002F\u002F 1=读, 0=写\n    input wire [N-1:0] Index,    \u002F\u002F 寄存器地址\n    input wire [M-1:0] DataIn,   \u002F\u002F 写入的数据\n    output reg [M-1:0] Dataout   \u002F\u002F 读出的数据\n);\n\n    \u002F\u002F 定义寄存器文件存储体 (内存)\n    \u002F\u002F 这是一个 M 位宽, 深度为 2^N 的数组\n    \u002F\u002F (N=2 => 2^2 = 4 个寄存器, 地址 0, 1, 2, 3)\n    reg [M-1:0] RegFile [ (2**N)-1 : 0 ];\n\n    always @(posedge Clk)\n    begin\n        if (Readwrite) \u002F\u002F 读\n        begin\n            \u002F\u002F 将 RegFile[Index] 的值锁存到 Dataout 寄存器\n            Dataout \u003C= RegFile[Index];\n        end else \u002F\u002F 写\n        begin\n            \u002F\u002F 将 DataIn 写入指定地址\n            RegFile[Index] \u003C= DataIn;\n        end\n    end\n\nendmodule\n",[328,586,584],{"__ignoreMap":360},[499,588],{},[311,590,591],{"id":591},"综合问题",[274,593,594],{"type":276},[270,595,596],{},"1 2 3 4 5 6 10 14 15 16 17 18 27 45 47 48 49 50",[320,598,599],{"id":599},"第一个",[270,601,602],{},[603,604],"img",{"alt":603,"src":605},"\u002Fimg\u002FHDL\u002FFeiQilai2-01.png",[270,607,608],{},[603,609],{"alt":603,"src":610},"\u002Fimg\u002FHDL\u002FFeiQilai2-02.png",[270,612,613],{},[328,614,615],{"code":615},"cAll = {cPartI[PartIMSB:0], {ExcludePartIBits{0}}};",[617,618,619],"ul",{},[346,620,621,624,625,628,629,628,632,635,636,639,640,643,644,647,648,650,651,654,655,658,659,662,663,666],{},[328,622,623],{"code":623},"{ExcludePartIBits{0}}","：这是一个复制(Replication) 操作。它的意思是“把 0 这个值，",[287,626,627],{},"复制"," ",[328,630,631],{"code":631},"ExcludePartIBits",[287,633,634],{},"次","”。\n但是 ",[328,637,638],{"code":638},"Value"," 是 ",[328,641,642],{"code":642},"0","，这是一个",[287,645,646],{},"“无大小的数字” (unsized literal)"," （这里无大小可以理解为没有告诉我是多少“位宽”的0）。意味着：Verilog 编译器不知道你希望这个 ",[328,649,642],{"code":642}," 是 1 比特 (",[328,652,653],{"code":653},"1'b0",")、8 比特 (",[328,656,657],{"code":657},"8'h00",") 还是 32 比特 (",[328,660,661],{"code":661},"32'd0",")。所以，编译器做出了一个默认的",[287,664,665],{},"假设","：“假设为32比特”。",[270,668,669,670,674],{},"这意味着，你的代码实际上在这里被解释为： ``cAll = {cPartI",[671,672,673],"span",{},"...",", {ExcludePartIBits{32'd0}}};```",[499,676],{},[320,678,679],{"id":679},"第二个",[270,681,682],{},[603,683],{"alt":603,"src":684},"\u002Fimg\u002FHDL\u002FFeiQilai2-03.png",[270,686,687],{},[603,688],{"alt":603,"src":689},"\u002Fimg\u002FHDL\u002FFeiQilai2-04.png",[270,691,692,693,696,697,700,701,704],{},"这个 ",[328,694,695],{"code":695},"always @ (...)"," 模块是用来描述一个",[287,698,699],{},"触发器","（就是能存数据的硬件）的。造这种硬件，综合工具（那个把代码变成硬件的程序）有个",[287,702,703],{},"死规定","：",[270,706,707,709,710,713,714,717],{},[328,708,370],{"code":370}," 模块里面",[287,711,712],{},"必须","是一个完整的 ",[328,715,716],{"code":716},"if...else..."," 结构，分成两半：",[343,719,720,728],{},[346,721,722,704,725],{},[287,723,724],{},"复位时干啥",[328,726,727],{"code":727},"if (!iReset) begin ... end",[346,729,730,704,733,736,737,740,741,743,744,747],{},[287,731,732],{},"平时干啥",[328,734,735],{"code":735},"else begin ... end","\n你所有的赋值 (",[328,738,739],{"code":739},"\u003C=",") 代码，",[287,742,712],{},"完整地放在这两个“块”的",[280,745,746],{},"里面","。",[270,749,750],{},"也就是这样",[354,752,755],{"className":753,"code":754,"language":359,"meta":360},[357],"always @ (posedge iClock or negedge iReset) begin\n\n    \u002F\u002F 情况一：处理复位\n    if (!iReset) begin\n        \u002F\u002F 所有的“复位”赋值必须在这里\n        \u002F\u002F (例如：reg_A \u003C= 0;)\n    end\n\n    \u002F\u002F 情况二：处理时钟\n    else begin \u002F\u002F 注意：这里是 else\n        \u002F\u002F 所有的“平时”赋值必须在这里\n        \u002F\u002F (例如：reg_A \u003C= data_in;)\n    end\n\n    \u002F\u002F *** 在这里不允许有任何赋值语句 ***\n\nend\n",[328,756,754],{"__ignoreMap":360},[270,758,759],{},"你错在哪里？",[270,761,762],{},"我们来看看你的“平时干啥”那部分：",[354,764,767],{"className":765,"code":766,"language":359,"meta":360},[357],"\u002F\u002F ...else if (iReset) begin   \u002F\u002F \u003C-- “平时干啥”的 { 开始if (ciRegMode == `CNormalMode)\n        rData \u003C= iData;\n    end \u002F\u002F \u003C-- 错误！你在这里就把“平时干啥”的 } 给关上了！\u002F\u002F 因为上面关早了，这行代码就“裸奔”在外面了\n    rRegMode \u003C= ciRegMode;\n\nend \u002F\u002F \u003C-- 这个 end 本来想配 always 的 begin\n",[328,768,766],{"__ignoreMap":360},[270,770,771],{},[287,772,773],{},"问题就出在这里：",[270,775,776,777,780,781,784,785,747],{},"那行 ",[328,778,779],{"code":779},"rRegMode \u003C= ciRegMode;"," 掉在了 ",[328,782,783],{"code":783},"else"," 块的",[287,786,787],{},"外面",[270,789,790,791,793],{},"它现在既不属于“复位时干啥”，也不属于“平时干啥”，它就这么“漂浮”在 ",[328,792,370],{"code":370}," 块里。",[270,795,796,797,378,800,802],{},"综合工具看到这行“漂浮”的代码，直接就懵了，它不知道该拿这行代码怎么办，因为它不符合“必须在 ",[328,798,799],{"code":799},"if",[328,801,783],{"code":783}," 块里”的规定。",[270,804,805,806,628,809,628,813],{},"总结：",[287,807,808],{},"always块中不允许在",[287,810,811],{},[328,812,370],{"code":370},[287,814,815],{},"块的“顶层”(也就是if-else块的外面)进行赋值，因为在综合的时候无法确定这个代码是在哪个阶段执行",[499,817],{},[320,819,821],{"id":820},"第三个",[337,822,820],{},[270,824,825],{},[603,826],{"alt":603,"src":827},"\u002Fimg\u002FHDL\u002FFeiQilai2-05.png",[270,829,830],{},[603,831],{"alt":603,"src":832},"\u002Fimg\u002FHDL\u002FFeiQilai2-06.png",[270,834,835],{},"这个问题非常经典！用一句话说清楚就是：",[270,837,838],{},[287,839,840],{},"你不能用一个“数据位”来当“时钟”用。",[270,842,843],{},[287,844,845],{},"详细解释（说人话）",[343,847,848,867,907],{},[346,849,850,628,855,858,859,862,863,866],{},[287,851,852],{},[328,853,854],{"code":854},"always @ (posedge ...)",[287,856,857],{},"是用来干嘛的？"," 这个语句是 Verilog 里用来造",[287,860,861],{},"时序逻辑","的，最常见的就是造",[287,864,865],{},"D触发器","（Flip-Flop）。D 触发器是硬件里用来存数据的基本单元，它需要一个“节拍器”来告诉它什么时候“存”。",[346,868,869,628,874,877,879,880,883,884,887,888],{},[287,870,871],{},[328,872,873],{"code":873},"posedge",[287,875,876],{},"后面应该放什么？",[328,878,873],{"code":873}," (上升沿) 后面，综合工具",[287,881,882],{},"期望","你放一个",[287,885,886],{},"“时钟信号” (Clock Signal)"," 。\n",[617,889,890,904],{},[346,891,892,895,896,899,900,903],{},[287,893,894],{},"时钟","是整个电路的“心跳”（比如 ",[328,897,898],{"code":898},"clk",", ",[328,901,902],{"code":902},"iClock","）。它是一个非常干净、稳定、有规律的“滴-答-滴-答”信号。",[346,905,906],{},"所有触发器都应该听同一个“心跳”信号，这样才能保证整个电路步调一致。",[346,908,909,912,913,916,917,920,921],{},[287,910,911],{},"你放了什么？"," 你放了 ",[328,914,915],{"code":915},"iData[pmt+2]","，也就是 ",[328,918,919],{"code":919},"iData[7]","。\n",[617,922,923,929],{},[346,924,925,928],{},[328,926,927],{"code":927},"iData"," 从名字上看就是**“数据” (Data)**。",[346,930,931,933],{},[328,932,919],{"code":919}," 只是这个数据总线上的第 7 根线。\n主要原因还是，时钟信号走的是专用的、高速的“时钟网络”（Global Clock Network），稳定，无毛刺",[270,935,936],{},"但是数据走的是“通用布线网络”（General Routing Fabric），会有毛刺，这样就会多次误触发always块",[499,938],{},[320,940,941],{"id":941},"第四个",[270,943,944],{},[603,945],{"alt":603,"src":946},"\u002Fimg\u002FHDL\u002FFeiQilai2-07.png",[270,948,949],{},[603,950],{"alt":603,"src":951},"\u002Fimg\u002FHDL\u002FFeiQilai2-08.png",[270,953,954],{},"简单来说，这个错误的意思是：",[270,956,957,960,628,965,972,628,977,628,984,989],{},[287,958,959],{},"在（老的）Verilog 语法里，如果",[337,961,962],{},[287,963,964],{},"一个",[337,966,967],{},[287,968,969],{},[328,970,971],{"code":971},"task",[337,973,974],{},[287,975,976],{},"（任务）没有输入或输出参数，那么在定义它或调用它的时候，你不能加",[337,978,979],{},[287,980,981],{},[328,982,983],{"code":983},"()",[337,985,986],{},[287,987,988],{},"括号",[287,990,747],{},[499,992],{},[320,994,995],{"id":995},"第五个",[270,997,998],{},[603,999],{"alt":603,"src":1000},"\u002Fimg\u002FHDL\u002FFeiQilai2-09.png",[270,1002,1003],{},[603,1004],{"alt":603,"src":1005},"\u002Fimg\u002FHDL\u002FFeiQilai2-10.png",[270,1007,1008],{},"简单来说，这个警告的意思是：",[270,1010,1011],{},[287,1012,1013],{},"你把“立即执行”的组合逻辑和“等一等再执行”的时序逻辑给混用了。",[270,1015,1016,1017,1020,1021,1023],{},"在 Verilog 里，",[328,1018,1019],{"code":1019},"="," 和 ",[328,1022,739],{"code":739}," 是两种完全不同的赋值：",[343,1025,1026,1073],{},[346,1027,1028,628,1032,1035],{},[287,1029,1030],{},[328,1031,1019],{"code":1019},[287,1033,1034],{},"(阻塞赋值 \u002F Blocking Assignment)",[617,1036,1037,1043,1059],{},[346,1038,1039,1042],{},[287,1040,1041],{},"意思是："," “马上办，立刻办！”",[346,1044,1045,1048,1049,1052,1053,378,1056,747],{},[287,1046,1047],{},"用途："," 用于",[287,1050,1051],{},"组合逻辑"," (Combinational Logic)，比如 ",[328,1054,1055],{"code":1055},"always @ (*)",[328,1057,1058],{"code":1058},"always @ (In)",[346,1060,1061,1064,1065,1068,1069,1072],{},[287,1062,1063],{},"行为："," 这一行代码会",[280,1066,1067],{},"立刻","执行，并且",[280,1070,1071],{},"卡住","后面的代码，直到它执行完。",[346,1074,1075,628,1079,1082],{},[287,1076,1077],{},[328,1078,739],{"code":739},[287,1080,1081],{},"(非阻塞赋值 \u002F Non-Blocking Assignment)",[617,1083,1084,1089,1099],{},[346,1085,1086,1088],{},[287,1087,1041],{}," “等一等，大家一起办。”",[346,1090,1091,1048,1093,1095,1096,747],{},[287,1092,1047],{},[287,1094,861],{}," (Sequential Logic)，比如 ",[328,1097,1098],{"code":1098},"always @ (posedge clk)",[346,1100,1101,1103,1104,1107],{},[287,1102,1063],{}," 这一行代码只是“登记”一个任务，说“我打算在当前时间片结束时更新这个值”。它",[280,1105,1106],{},"不会","卡住后面的代码\n带有task块的代码等价过程",[354,1109,1112],{"className":1110,"code":1111,"language":359,"meta":360},[357],"always@(In)   \n    tShift(Out, In); \u002F\u002F \u003C-- 这是“调用点”\n    task \n        tShift(output Q, input D); \u002F\u002F \u003C-- 这是“定义”   \n        Q \u003C= D; \n    endtask\n\n\u002F\u002F 等价之后\n\nalways@(In)   \n    Q \u003C= In;  \u002F\u002F 冲突点就在这里了\n",[328,1113,1111],{"__ignoreMap":360},[270,1115,1116],{},[287,1117,1118],{},"这就是矛盾所在：",[617,1120,1121,1139],{},[346,1122,1123,1124,1126,1127,1130,1131,1134,1135,1138],{},"你的 ",[328,1125,1058],{"code":1058}," 模块期望 ",[328,1128,1129],{"code":1129},"Out"," 的值在 ",[328,1132,1133],{"code":1133},"In"," 变化时",[287,1136,1137],{},"立即","更新。",[346,1140,1141,1142,1144,1145,1148,1149,1152,1153,1156,1157,1159,1160],{},"但你调用的 ",[328,1143,971],{"code":971}," 里面却使用了 ",[328,1146,1147],{"code":1147},"Q \u003C= D;","（也就是 ",[328,1150,1151],{"code":1151},"Out \u003C= In;","），这会告诉仿真器：“别急，我",[287,1154,1155],{},"等会儿","（到这个时间片末尾）再更新 ",[328,1158,1129],{"code":1129}," 的值。”\n",[287,1161,1162],{},"为什么这会导致“模拟失败”？",[270,1164,1165],{},"因为这制造了一个“竞争条件” (Race Condition)。",[270,1167,1168,1169,1171],{},"想象一下，在同一个仿真时间点，有另一块逻辑需要读取 ",[328,1170,1129],{"code":1129}," 的值。它读到的是：",[617,1173,1174,1183],{},[346,1175,1176,1178,1179,1182],{},[328,1177,1133],{"code":1133}," 变化",[287,1180,1181],{},"之前","的旧值？",[346,1184,1185,1186,1178,1188,1191,1192],{},"还是 ",[328,1187,1133],{"code":1133},[287,1189,1190],{},"之后","的新值？\n答案是：",[287,1193,1194],{},"不确定！",[499,1196],{},[320,1198,1199],{"id":1199},"第六个",[270,1201,1202],{},[603,1203],{"alt":603,"src":1204},"\u002Fimg\u002FHDL\u002FFeiQilai2-11.png",[270,1206,1207],{},[603,1208],{"alt":603,"src":1209},"\u002Fimg\u002FHDL\u002FFeiQilai2-12.png",[270,1211,1212],{},"这个警告（Warning）的意思非常直白：",[270,1214,1215,628,1218,628,1223,628,1226,628,1230],{},[287,1216,1217],{},"“你定义了一个名叫",[287,1219,1220],{},[328,1221,1222],{"code":1222},"undriven_out",[287,1224,1225],{},"的输出口，但是在",[287,1227,1228],{},[328,1229,971],{"code":971},[287,1231,1232],{},"里面你一次都没给它赋过值。”",[270,1234,1235,1236],{},"task其实非常像C或者Python中的函数，里面的input和output就可以看作他的参数，在这一道题里面，我如果在别的地方，在某个always块中通过maybeUnconnected(my_input_wire, my_output_reg_A, my_output_reg_B);调用这个task时，就会出现my_output_reg_B没有对应的情况（因为只有这个out是明确有输出的）\n所以，",[287,1237,1238],{},"如果我不需要这个输出，要么我就不定义，要么我必须在task里面指定为0（也就是接地",[499,1240],{},[320,1242,1243],{"id":1243},"第十个",[270,1245,1246],{},[603,1247],{"alt":603,"src":1248},"\u002Fimg\u002FHDL\u002FFeiQilai2-13.png",[270,1250,1251],{},[603,1252],{"alt":603,"src":1253},"\u002Fimg\u002FHDL\u002FFeiQilai2-14.png",[270,1255,1008],{},[270,1257,1258,628,1261,1266,628,1269,628,1273,1276,628,1280],{},[287,1259,1260],{},"“你的代码在读取",[287,1262,1263],{},[328,1264,1265],{"code":1265},"in2",[287,1267,1268],{},"，但你忘了告诉",[287,1270,1271],{},[328,1272,370],{"code":370},[287,1274,1275],{},"块去‘监听’",[287,1277,1278],{},[328,1279,1265],{"code":1265},[287,1281,1282],{},"的变化。”",[270,1284,1285,1286,1289,1290,1293],{},"因为从",[328,1287,1288],{"code":1288},"myout = in1 | in2","可以看出，这个是",[287,1291,1292],{},"组合逻辑，但是代码在组合逻辑中，没有把每一个被读取的信号加到敏感表里面","，这样会产生锁存器，所以导致了错误",[499,1295],{},[320,1297,1298],{"id":1298},"第十四个",[270,1300,1301],{},[603,1302],{"alt":603,"src":1303},"\u002Fimg\u002FHDL\u002FFeiQilai2-15.png",[270,1305,1306],{},[603,1307],{"alt":603,"src":1308},"\u002Fimg\u002FHDL\u002FFeiQilai2-16.png",[270,1310,1311,1312,628,1315,628,1319],{},"这个警告是在提醒你：",[287,1313,1314],{},"你的",[287,1316,1317],{},[328,1318,471],{"code":471},[287,1320,1321],{},"语句写得“不完整”，这可能会让综合工具（Synopsys）造出一个又大又慢的电路。",[270,1323,1324],{},"过一遍case代码，这个的逻辑是：",[617,1326,1327,1341,1351,1365],{},[346,1328,1329,1330,1333,1334,1337,1338,747],{},"当 ",[328,1331,1332],{"code":1332},"c"," = ",[328,1335,1336],{"code":1336},"2'b00"," 时，",[328,1339,1340],{"code":1340},"out = in1",[346,1342,1329,1343,1333,1345,1337,1348,747],{},[328,1344,1332],{"code":1332},[328,1346,1347],{"code":1347},"2'b11",[328,1349,1350],{"code":1350},"out = in2",[346,1352,1329,1353,1333,1355,1337,1358,1360,1361,1364],{},[328,1354,1332],{"code":1332},[328,1356,1357],{"code":1357},"2'b01",[328,1359,1350],{"code":1350}," (来自 ",[328,1362,1363],{"code":1363},"default",")。",[346,1366,1329,1367,1333,1369,1337,1372,1360,1374,1376,1377,628,1382],{},[328,1368,1332],{"code":1332},[328,1370,1371],{"code":1371},"2'b10",[328,1373,1350],{"code":1350},[328,1375,1363],{"code":1363},")。\n",[287,1378,1379],{},[328,1380,1381],{"code":1381},"2'b11: out = in2;",[287,1383,1384],{},"这一行是完全多余的",[270,1386,1387,1389,1390,1393,1394,1397,1398,899,1400,899,1402,628,1405,1409],{},[328,1388,1363],{"code":1363}," 分支的 ",[328,1391,1392],{"code":1392},"out = in2;"," 已经",[287,1395,1396],{},"完全覆盖","了 ",[328,1399,1357],{"code":1357},[328,1401,1371],{"code":1371},[287,1403,1404],{},"和",[287,1406,1407],{},[328,1408,1347],{"code":1347}," 这三种情况。",[270,1411,1412,1413],{},"所以对应的最优硬件（一个2选1 MUX）应该是： ",[328,1414,1415],{"code":1415},"assign out = (c == 2'b00) ? in1 : in2;",[270,1417,1418],{},[287,1419,1420],{},"这个算是警告，也就是说可以生成更好的逻辑",[499,1422],{},[320,1424,1425],{"id":1425},"第十五个",[270,1427,1428],{},[603,1429],{"alt":603,"src":1430},"\u002Fimg\u002FHDL\u002FFeiQilai2-17.png",[270,1432,1433],{},[603,1434],{"alt":603,"src":1435},"\u002Fimg\u002FHDL\u002FFeiQilai2-18.png",[270,1437,1438,1439,628,1442,1445,1446,1449],{},"Verilog ",[287,1440,1441],{},"明确允许",[328,1443,1444],{"code":1444},"Z","可参与逻辑运算（它会被视为 ",[328,1447,1448],{"code":1448},"X","）。",[270,1451,1452,1455,1456,1459,1460,1462,1463,1466],{},[287,1453,1454],{},"这是糟糕的设计 (Bad Design)："," 在数字逻辑中，你",[287,1457,1458],{},"永远不应该","有意地去“与”一个高阻态。",[328,1461,1444],{"code":1444}," 的唯一正确用途是",[287,1464,1465],{},"描述一个“未驱动”状态","，通常用在三态门（Tri-state Buffer）中，以允许多个设备共享一条总线。",[270,1468,1469],{},[287,1470,1471],{},"正确用法 (Correct Use of Z)：",[354,1473,1476],{"className":1474,"code":1475,"language":359,"meta":360},[357],"\u002F\u002F 这是一个三态驱动器\n\u002F\u002F 当 enable = 1, out 被 data 驱动\n\u002F\u002F 当 enable = 0, out 被\"断开\"，呈现高阻态 Z\nassign out = (enable) ? data : 1'bz;\n",[328,1477,1475],{"__ignoreMap":360},[270,1479,1480],{},[603,1481],{"alt":603,"src":1482},"\u002Fimg\u002FHDL\u002FFeiQilai2-19.png",[274,1484,1485,1488],{"type":276},[270,1486,1487],{},"总之就是无法被综合or被优化，具体优化成什么实际上由具体软件决定",[270,1489,1490],{},[337,1491,1492],{},"神的旨意是不能综合",[499,1494],{},[320,1496,1497],{"id":1497},"第十六个",[270,1499,1500],{},[603,1501],{"alt":603,"src":1502},"\u002Fimg\u002FHDL\u002FFeiQilai2-20.png",[270,1504,1505],{},[603,1506],{"alt":603,"src":1507},"\u002Fimg\u002FHDL\u002FFeiQilai2-21.png",[270,1509,1510],{},"这个警告是 Verilog 中一个非常重要且危险的规则：",[270,1512,1513,628,1518,628,1524,628,1529,1536,628,1541,1548,628,1553,1560],{},[337,1514,1515],{},[287,1516,1517],{},"“在",[337,1519,1520],{},[287,1521,1522],{},[328,1523,799],{"code":799},[337,1525,1526],{},[287,1527,1528],{},"语句中，任何包含",[337,1530,1531],{},[287,1532,1533],{},[328,1534,1535],{"code":1535},"x",[337,1537,1538],{},[287,1539,1540],{},"（未知）或",[337,1542,1543],{},[287,1544,1545],{},[328,1546,1547],{"code":1547},"z",[337,1549,1550],{},[287,1551,1552],{},"（高阻）的条件都会被当作",[337,1554,1555],{},[287,1556,1557],{},[328,1558,1559],{"code":1559},"false",[337,1561,1562],{},[287,1563,1564],{},"（假）来处理。”",[270,1566,1567,1568,1570,1571,378,1573,1575,1576,1578,1579,378,1581,1584,1585,1587,1588,1591,1592,1595,1600,1603,1608],{},"在 ",[328,1569,799],{"code":799}," 语句中使用了 ",[328,1572,1535],{"code":1535},[328,1574,1547],{"code":1547},"。仿真器会把它们当 ",[328,1577,1559],{"code":1559}," 处理，而综合器会把它们当 ",[328,1580,642],{"code":642},[328,1582,1583],{"code":1583},"1"," 处理，这会导致仿真和硬件不一致。",[328,1586,1535],{"code":1535}," 的目的是在仿真中",[287,1589,1590],{},"传播“未知”","，以帮助",[287,1593,1594],{},"发现 bug，它的存在是为了",[287,1596,1597],{},[280,1598,1599],{},"暴露",[287,1601,1602],{},"问题，而不是用来",[287,1604,1605],{},[280,1606,1607],{},"设计",[287,1609,1610],{},"逻辑的",[499,1612],{},[343,1614,1615,1630,1680],{},[346,1616,1617,1620,1623,1624,1626,1627,1629],{},[287,1618,1619],{},"你的代码：",[328,1621,1622],{"code":1622},"if (2'b0x)"," 这是一个 2 比特的数，其中一位是 ",[328,1625,642],{"code":642},"，另一位是 ",[328,1628,1535],{"code":1535},"（未知）。",[346,1631,1632,1635,1637,1638],{},[287,1633,1634],{},"Verilog 的规则：",[328,1636,799],{"code":799}," 语句在判断“真”或“假”时，规则如下：\n",[617,1639,1640,1660],{},[346,1641,1642,1645,1646,1649,1650,1652,1653,1656,1657,1659],{},[287,1643,1644],{},"真 (True)："," 只有当",[287,1647,1648],{},"所有位","都明确是 ",[328,1651,642],{"code":642}," 时，才为假。只要有",[287,1654,1655],{},"任何一位","是 ",[328,1658,1583],{"code":1583},"，就为真。",[346,1661,1662,1665,1666,1656,1668,378,1670,1672,1673,628,1676,747],{},[287,1663,1664],{},"假 (False)："," 如果",[287,1667,1655],{},[328,1669,1535],{"code":1535},[328,1671,1547],{"code":1547},"，那么整个条件",[287,1674,1675],{},"立即被判为",[287,1677,1678],{},[328,1679,1559],{"code":1559},[346,1681,1682,1685],{},[287,1683,1684],{},"代码的行为：",[617,1686,1687,1702,1720,1732],{},[346,1688,1689,1690,1693,1694,1696,1697,1699,1700,747],{},"因为你的条件 ",[328,1691,1692],{"code":1692},"2'b0x"," 包含了一个 ",[328,1695,1535],{"code":1535},"，",[328,1698,799],{"code":799}," 语句立即将其判为 ",[328,1701,1559],{"code":1559},[346,1703,1704,1705,1707,1708,1711,1712,1715,1716,1719],{},"所以，",[328,1706,799],{"code":799}," 后面的第一个 ",[328,1709,1710],{"code":1710},"begin...end"," 块（",[328,1713,1714],{"code":1714},"out = in1;","）",[287,1717,1718],{},"永远不会","被执行。",[346,1721,1722,1724,1725,1711,1727,1715,1729,1719],{},[328,1723,783],{"code":783}," 后面的 ",[328,1726,1710],{"code":1710},[328,1728,1392],{"code":1392},[287,1730,1731],{},"永远都会",[346,1733,1734,1735,1020,1738,1741],{},"（你代码中的注释 ",[328,1736,1737],{"code":1737},"\u002F* Will never fire *\u002F",[328,1739,1740],{"code":1740},"\u002F* Will always fire *\u002F"," 已经完美地指出了这一点。）\n你可能会想：“既然我知道它永远是 false，这不就行了吗？”",[270,1743,1744,1747,1748,1751],{},[287,1745,1746],{},"不行，这非常危险！"," 这就是警告中“",[287,1749,1750],{},"模拟\u002F综合不匹配","”的来源：",[343,1753,1754,1795],{},[346,1755,1756,1759],{},[287,1757,1758],{},"模拟 (Simulation) 怎么看：",[617,1760,1761,1768,1776],{},[346,1762,1763,1764,1767],{},"你的仿真器（比如 VCS, Modelsim）会",[287,1765,1766],{},"严格遵守","上面的 Verilog 规则。",[346,1769,1770,1771,1773,1774,747],{},"它看到 ",[328,1772,1535],{"code":1535},"，就判为 ",[328,1775,1559],{"code":1559},[346,1777,1778,1779,1782,1783,628,1786,1789,1790,1792,1793,747],{},"所以在你所有的",[287,1780,1781],{},"仿真测试","中，",[328,1784,1785],{"code":1785},"out",[287,1787,1788],{},"永远","等于 ",[328,1791,1265],{"code":1265},"。你的测试结果会显示电路的功能就是 ",[328,1794,1392],{"code":1392},[346,1796,1797,1800],{},[287,1798,1799],{},"综合 (Synthesis) 怎么看：",[617,1801,1802,1809,1818,1828,1851],{},[346,1803,1804,1805,1808],{},"综合工具（比如 Synopsys DC, Vivado）是用来",[287,1806,1807],{},"造硬件","的。",[346,1810,1811,1812,1814,1815,747],{},"当它看到 ",[328,1813,1535],{"code":1535},"，它会把它理解为 ",[287,1816,1817],{},"\"don't care\"（不关心）",[346,1819,1820,1821,1823,1824,1827],{},"它会想：“哦，设计师不关心 ",[328,1822,1535],{"code":1535}," 这种情况。太好了！我可以利用这个‘不关心’来",[287,1825,1826],{},"优化电路","，让它变得最小、最快！”",[346,1829,1830,1833,1834,1837,1838,1840,1841,1843,1844,1847,1848,1850],{},[287,1831,1832],{},"灾难来了："," 为了优化，综合工具",[287,1835,1836],{},"可能","会把 ",[328,1839,1535],{"code":1535}," 当作 ",[328,1842,1583],{"code":1583}," 来处理（如果 ",[328,1845,1846],{"code":1846},"if (2'b01)"," 能让电路更简单的话），也可能把它当 ",[328,1849,642],{"code":642}," 来处理。",[346,1852,1853,1854,1840,1856,1858,1859,920,1861,1864,1865,1868,1869,1871,1872,1875,1876,1878],{},"如果它把 ",[328,1855,1535],{"code":1535},[328,1857,1583],{"code":1583}," 来优化，它造出的硬件就会在某些情况下执行 ",[328,1860,1714],{"code":1714},[287,1862,1863],{},"最终结果："," 你",[287,1866,1867],{},"测试","的电路（仿真）表现为 ",[328,1870,1392],{"code":1392},"。 你",[287,1873,1874],{},"造出","的芯片（综合）表现为 ",[328,1877,1714],{"code":1714}," (在某些情况下)。",[270,1880,1881],{},[287,1882,1883],{},"你的芯片和你的测试完全对不上，这就是“模拟\u002F综合不匹配”，它是硬件开发中最致命的 bug 之一。",[270,1885,1886,1889,1890,378,1892,1894,1895,378,1897,747],{},[287,1887,1888],{},"结论："," 永远不要在 ",[328,1891,799],{"code":799},[328,1893,471],{"code":471}," 语句的条件中（即控制逻辑中）使用 ",[328,1896,1535],{"code":1535},[328,1898,1547],{"code":1547},[320,1900,1901],{"id":1901},"第十七个",[270,1903,1904],{},[603,1905],{"alt":603,"src":1906},"\u002Fimg\u002FHDL\u002FFeiQilai2-22.png",[270,1908,1909],{},[603,1910],{"alt":603,"src":1911},"\u002Fimg\u002FHDL\u002FFeiQilai2-23.png",[270,1913,1914],{},"这个警告的意思非常简单：",[270,1916,1917,628,1919,628,1923],{},[287,1918,1314],{},[287,1920,1921],{},[328,1922,1363],{"code":1363},[287,1924,1925],{},"语句是多余的，它永远不会被执行。",[499,1927],{},[320,1929,1930],{"id":1930},"第十八个",[270,1932,1933],{},[603,1934],{"alt":603,"src":1935},"\u002Fimg\u002FHDL\u002FFeiQilai2-24.png",[270,1937,1938],{},[603,1939],{"alt":603,"src":1940},"\u002Fimg\u002FHDL\u002FFeiQilai2-25.png",[270,1942,1943],{},[328,1944,1945],{"code":1945},"b: y = ~a;",[270,1947,1948],{},[328,1949,1950],{"code":1950},"default: y = b;",[270,1952,1953],{},"不会被执行",[270,1955,1956,1957],{},"其实主要还是因为这个case语句里面直接放了一个常量",[328,1958,1959],{"code":1959},"1'b1",[499,1961],{},[320,1963,1964],{"id":1964},"第二十七个",[270,1966,1967],{},[603,1968],{"alt":603,"src":1969},"\u002Fimg\u002FHDL\u002FFeiQilai2-26.png",[270,1971,1972],{},[603,1973],{"alt":603,"src":1974},"\u002Fimg\u002FHDL\u002FFeiQilai2-27.png",[270,1976,1977,1978,628,1981,628,1985,628,1988,628,1993],{},"简单来说：",[287,1979,1980],{},"你的两个",[287,1982,1983],{},[328,1984,370],{"code":370},[287,1986,1987],{},"块在“抢夺”同一个变量",[287,1989,1990],{},[328,1991,1992],{"code":1992},"i",[287,1994,1995],{},"的“控制权”。",[270,1997,1998,1999],{},"主要的原因就是，",[287,2000,2001],{},"这两个always块是同步直接执行的，然后因为这个同步的问题，所以不能同时对一样的 i 进行赋值",[320,2003,2004],{"id":2004},"第四十五个",[270,2006,2007],{},[603,2008],{"alt":603,"src":2009},"\u002Fimg\u002FHDL\u002FFeiQilai2-28.png",[270,2011,2012],{},"代码45：（错误）使用空参数列表进行非法函数声明。",[270,2014,2015,2018,2019,1696,2022,2025,628,2030,2035,2036,628,2038,2041],{},[328,2016,2017],{"code":2017},"function","（函数）在 Verilog 中有严格的用途：它必须是一个",[287,2020,2021],{},"纯粹的组合逻辑",[337,2023,2024],{},"它接受",[337,2026,2027],{},[287,2028,2029],{},"至少一个",[337,2031,2032],{},[328,2033,2034],{"code":2034},"input","，并根据这些 ",[328,2037,2034],{"code":2034},[287,2039,2040],{},"计算出一个返回值（output只有一个）","。所以不能为空参数",[499,2043],{},[320,2045,2046],{"id":2046},"第四十七个",[270,2048,2049],{},[603,2050],{"alt":603,"src":2051},"\u002Fimg\u002FHDL\u002FFeiQilai2-29.png",[270,2053,2054],{},[603,2055],{"alt":603,"src":2056},"\u002Fimg\u002FHDL\u002FFeiQilai2-30.png",[270,2058,2059,2060,2062,2063,2065],{},"我的理解是：",[328,2061,2017],{"code":2017}," 必须在 0 时间内立即执行完毕，而 ",[328,2064,971],{"code":971}," 可以消耗时间",[270,2067,2068],{},"所以：",[617,2070,2071,2074],{},[346,2072,2073],{},"在function当中不能调用task",[346,2075,2076],{},"但是在task中可以调用function\n简单来说：",[270,2078,2079,2082,2086,2089,2093],{},[287,2080,2081],{},"函数 (",[287,2083,2084],{},[328,2085,2017],{"code":2017},[287,2087,2088],{},") 必须像数学公式一样“立即”算出一个结果，而任务 (",[287,2090,2091],{},[328,2092,971],{"code":971},[287,2094,2095],{},") 可能会“花时间等待”。Verilog 不允许一个“立即”的东西去调用一个“可能要等待”的东西。",[499,2097],{},[2099,2100,2101,2117],"table",{},[2102,2103,2104],"thead",{},[2105,2106,2107,2111,2114],"tr",{},[2108,2109,2110],"th",{},"特性",[2108,2112,2113],{},"函数 (Function)",[2108,2115,2116],{},"任务 (Task)",[2118,2119,2120,2132,2143,2154,2165,2176,2186],"tbody",{},[2105,2121,2122,2126,2129],{},[2123,2124,2125],"td",{},"事件控制",[2123,2127,2128],{},"不能包含任何事件控制语句（如 @、#、wait）。",[2123,2130,2131],{},"可以包含事件控制语句。",[2105,2133,2134,2137,2140],{},[2123,2135,2136],{},"执行时间",[2123,2138,2139],{},"必须在 0 模拟时间内执行完毕。",[2123,2141,2142],{},"可以在非 0 模拟时间内执行。",[2105,2144,2145,2148,2151],{},[2123,2146,2147],{},"端口",[2123,2149,2150],{},"必须至少有 1 个 input 端口，且只有 1 个 output 端口。",[2123,2152,2153],{},"可以有 0 个或多个 input、output 或 inout 类型的端口。",[2105,2155,2156,2159,2162],{},[2123,2157,2158],{},"调用",[2123,2160,2161],{},"只能调用其他函数。",[2123,2163,2164],{},"可以调用其他任务或函数。",[2105,2166,2167,2170,2173],{},[2123,2168,2169],{},"主要用途",[2123,2171,2172],{},"相对易于综合。常用于简化组合逻辑的表述或进行编译时常量计算。",[2123,2174,2175],{},"描述更复杂的行为，相对较难综合。",[2105,2177,2178,2181,2184],{},[2123,2179,2180],{},"局部变量",[2123,2182,2183],{},"默认是静态的 (static)，在所有调用中共享。可使用 automatic 关键字使其非共享。",[2123,2185,2183],{},[2105,2187,2188,2191,2194],{},[2123,2189,2190],{},"返回值",[2123,2192,2193],{},"默认输出返回 1 位 reg 类型。可以使用 return 语句返回值。",[2123,2195,2196],{},"可以使用 return 语句返回。",[320,2198,2199],{"id":2199},"第四十八个",[270,2201,2202],{},[603,2203],{"alt":603,"src":2204},"\u002Fimg\u002FHDL\u002FFeiQilai2-31.png",[270,2206,2207],{},[603,2208],{"alt":603,"src":2209},"\u002Fimg\u002FHDL\u002FFeiQilai2-32.png",[270,2211,2212,2213],{},"在task里面，",[287,2214,2215],{},"如果内部有一个output，那么在调用该task时，就需要传入某一个变量，这个变量是用来被赋值的",[270,2217,2218],{},"这个错误非常直观，简单来说就是：",[270,2220,2221,628,2226],{},[287,2222,2223],{},[328,2224,2225],{"code":2225},"output",[287,2227,2228],{},"端口是用来“往外写数据”的（驱动器），你必须给它一个“变量”来接住数据，但你却给了一个“常量”。",[499,2230],{},[320,2232,2233],{"id":2233},"第四十九个",[270,2235,2236],{},[603,2237],{"alt":603,"src":2238},"\u002Fimg\u002FHDL\u002FFeiQilai2-33.png",[270,2240,2241],{},[603,2242],{"alt":603,"src":2243},"\u002Fimg\u002FHDL\u002FFeiQilai2-34.png",[270,2245,2246,2247,2250],{},"这个问题和您刚才问的“代码48”是",[287,2248,2249],{},"一模一样的根本错误","，只是换了一种形式。",[270,2252,2253,2254,2257,2258],{},"具体理解就是，",[287,2255,2256],{},"wire","因为是线网型，不能被当作一个变量，因为",[287,2259,2260],{},"wire是只读的",[270,2262,1977],{},[270,2264,2265,628,2269,628,2272,628,2276,2279,2283,2286,628,2291],{},[287,2266,2267],{},[328,2268,971],{"code":971},[287,2270,2271],{},"的",[287,2273,2274],{},[328,2275,2225],{"code":2225},[287,2277,2278],{},"端口（",[287,2280,2281],{},[328,2282,1535],{"code":1535},[287,2284,2285],{},"）需要一个“篮子”（",[287,2287,2288],{},[328,2289,2290],{"code":2290},"reg",[287,2292,2293],{},"变量）来存放它要输出的值。但你却给了它一个“只读”的东西。",[499,2295],{},[320,2297,2298],{"id":2298},"第五十个",[270,2300,2301],{},[603,2302],{"alt":603,"src":2303},"\u002Fimg\u002FHDL\u002FFeiQilai2-35.png",[270,2305,2306],{},[603,2307],{"alt":603,"src":2308},"\u002Fimg\u002FHDL\u002FFeiQilai2-36.png",[270,2310,2311,2312],{},"这个错误是说：",[287,2313,2314],{},"你不能在“赋值语句”的中间“等待”一个事件。",[270,2316,2317,2318,2321,2322,2325,2326,2329,2330,628,2333,2335,2336,628,2339,2342,2343,2346,2347,2350],{},"这段代码",[287,2319,2320],{},"描述了一个行为","，而不是一个结构。它告诉",[287,2323,2324],{},"仿真器","：“请",[287,2327,2328],{},"暂停","在这里，",[287,2331,2332],{},"等待",[328,2334,898],{"code":898}," 的下一个上升沿出现。当它出现后，",[287,2337,2338],{},"读取",[328,2340,2341],{"code":2341},"a"," 的值，然后",[287,2344,2345],{},"赋值","给 ",[328,2348,2349],{"code":2349},"y","。”",[270,2352,2353,628,2356,2359,2360,2362],{},[287,2354,2355],{},"问题：",[287,2357,2358],{},"物理硬件无法“暂停”","。一个“与”门不能说“我先不工作了，等个时钟沿再算”。硬件是",[287,2361,1788],{},"在运行的。所以综合上会有问题",[270,2364,2365],{},[287,2366,2367],{},"正确的代码：",[270,2369,2370],{},"Verilog",[354,2372,2377],{"className":2373,"code":2375,"language":2376},[2374],"language-text","\u002F\u002F 这是一个标准的 D 触发器\u002F\u002F 它描述了一个“硬件结构”\nalways @ (posedge clk) begin\n    y \u003C= a;\nend\n","text",[328,2378,2375],{"__ignoreMap":360},{"title":360,"searchDepth":405,"depth":405,"links":2380},[2381,2397],{"id":313,"depth":365,"text":313,"children":2382},[2383,2390],{"id":322,"depth":391,"text":323,"children":2384},[2385,2386,2387,2388,2389],{"id":335,"depth":405,"text":335},{"id":425,"depth":405,"text":426},{"id":442,"depth":405,"text":443},{"id":458,"depth":405,"text":461},{"id":481,"depth":405,"text":484},{"id":503,"depth":391,"text":504,"children":2391},[2392,2393,2394,2395,2396],{"id":507,"depth":405,"text":510},{"id":530,"depth":405,"text":530},{"id":542,"depth":405,"text":543},{"id":555,"depth":405,"text":556},{"id":572,"depth":405,"text":573},{"id":591,"depth":365,"text":591,"children":2398},[2399,2400,2401,2402,2403,2404,2405,2406,2407,2408,2409,2410,2411,2412,2413,2414,2415,2416],{"id":599,"depth":391,"text":599},{"id":679,"depth":391,"text":679},{"id":820,"depth":391,"text":820},{"id":941,"depth":391,"text":941},{"id":995,"depth":391,"text":995},{"id":1199,"depth":391,"text":1199},{"id":1243,"depth":391,"text":1243},{"id":1298,"depth":391,"text":1298},{"id":1425,"depth":391,"text":1425},{"id":1497,"depth":391,"text":1497},{"id":1901,"depth":391,"text":1901},{"id":1930,"depth":391,"text":1930},{"id":1964,"depth":391,"text":1964},{"id":2004,"depth":391,"text":2004},{"id":2046,"depth":391,"text":2046},{"id":2199,"depth":391,"text":2199},{"id":2233,"depth":391,"text":2233},{"id":2298,"depth":391,"text":2298},[228],"HDL 期末复习：典型代码（全加器、移位器、D 触发器、计数器）与综合问题解析","md",null,{"slots":2422},{},{"text":2424,"minutes":2425,"time":2426,"words":2427},"29 min read",28.755,1725300,5751,{"title":191,"description":2418},{"loc":190,"images":2430},[2431,2432,2433,2434,2435,2436,2437,2438,2439,2440,2441,2442,2443,2444,2445,2446,2447,2448,2449,2450,2451,2452,2453,2454,2455,2456,2457,2458,2459,2460,2461,2462,2463,2464,2465,2466],{"loc":605},{"loc":610},{"loc":684},{"loc":689},{"loc":827},{"loc":832},{"loc":946},{"loc":951},{"loc":1000},{"loc":1005},{"loc":1204},{"loc":1209},{"loc":1248},{"loc":1253},{"loc":1303},{"loc":1308},{"loc":1430},{"loc":1435},{"loc":1482},{"loc":1502},{"loc":1507},{"loc":1906},{"loc":1911},{"loc":1935},{"loc":1940},{"loc":1969},{"loc":1974},{"loc":2009},{"loc":2051},{"loc":2056},{"loc":2204},{"loc":2209},{"loc":2238},{"loc":2243},{"loc":2303},{"loc":2308},[2468,2469,2470],"期末复习","HDL","课程笔记","tech","Ohi9hElnVhCnb2s-Cv-o8YM-I4PWjg5_tWAp83BYO1Y",[2474,2475],{"title":186,"path":185,"stem":184,"date":187,"type":2471,"children":-1},{"title":196,"path":195,"stem":194,"date":197,"type":2471,"children":-1},1789037802065]